`timescale 1ns/1ns 
module elock ();
  reg clk;
  reg rst;
  reg clk_disp;
  wire  [3:0] h2;
  wire  [3:0] h1;
  wire  [3:0] m2;
  wire  [3:0] m1;
  wire  [3:0] s2;
  wire  [3:0] s1;
  // 时钟初始化
initial
  begin
    clk=1'b0;
    rst=1'b0;
  end
 
  always #5 clk = ~clk;
  
  // hmst 实例化
  hms hmst (
   // .clk_disp(clk_disp),
    .clk(clk),
	  .rst(rst),
	  .h1(h1),
	  .h2(h2),
	  .m1(m1),
	  .m2(m2),
	  .s1(s1),
	  .s2(s2)
  );
  
endmodule